DS1308U-3+【PDF 15/16 页】IC RTC 56BYTE NVRAM I2C 8UMAX

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DS1308

Low-Current I2C RTC with 56-Byte NV RAM

Maxim Integrated

Functional Diagram

Detailed Description

The DS1308 serial RTC is a low-power, full BCD clock/

calendar plus 56 bytes of NV SRAM. Address and data

are transferred serially through an I2C interface. The

clock/calendar provides seconds, minutes, hours, day,

date, month, and year information. The end of the month

date is automatically adjusted for months with fewer than

31 days, including corrections for leap year. The clock

operates in either the 24-hour or 12-hour format with an

AM/PM indicator. The DS1308 has a built-in power-sense

circuit that detects power failures and automatically

switches to the VBAT supply.

Operation

The DS1308 operates as a slave device on the serial bus.

Access is obtained by implementing a START condition

and providing a device identification code, followed by

data. Subsequent registers can be accessed sequen-

tially until a STOP condition is executed. The device is

fully accessible and data can be written and read when

VCC is greater than VPF. However, when VCC falls below

VPF, the internal clock registers are blocked from any

access. If VBAT is greater than VCC, the device power is

switched from VCC to VBAT when VCC drops below VPF.

If VBAT is less than VPF, the device power is switched

from VCC to VBAT when VCC drops below VBAT. The

oscillator and timekeeping functions are maintained

from the VBAT source until VCC returns above VPF, read

and write access is allowed after tREC. The Functional

Diagram shows the main elements of the DS1308.

An enable bit in the seconds register (CH) controls the

oscillator. Oscillator startup times are highly dependent

upon crystal characteristics, PCB leakage, and layout.

High ESR and excessive capacitive loads are the major

contributors to long startup times. A circuit using a crystal

with the recommended characteristics and proper layout

usually starts within 1 second.

On the first application of power to the device, the time

and date registers are reset to 01/01/00 01 00:00:00 (DD/

MM/YY DOW HH:MM:SS), and CH bit in the seconds

DS1308

/32

EXTSYNC

CONTROL LOGIC

OSC-1Hz

POWER CONTROL

RAM

CLOCK AND

CALENDAR REGISTERS

128Hz

OSC-1Hz

SQW/CLKIN

SCL

SDA

4.096kHz

8.192kHz

32.768kHz

MUX/

BUFFER

DIVIDER

EXT-1Hz

SERIAL BUS

INTERFACE AND

ADDRESS

VCC

VBAT

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